In the traditional display device, the scanning drive of the display module part usually controls the gate driving circuit through a piece of signal processing chip, thereby transmitting the gate driving signal to the display panel according to a preset time sequence, and therefore no synchronization problem exists therein. However, in the display product with large size or high resolution, a single chip is usually unable to finish the scanning drive for the whole display panel because it needs to process large amount of signals at the same time, and thus a plurality of chips are usually used to perform the scanning drive for different display areas at the same time. Therefore, the coordination among the plurality of chips is especially important.
In the conventional chip design, in order to realize the coordination among a plurality of chips, a frame memory unit is usually added to each chip, and frame memory units of each two chips communicate through signals of a serial peripheral interface bus (referred to as SPI) at the same time, so that each two chips work synchronously. The synchronized process specifically is as follows: a picture with more than one frame is pre-stored in the two chips, and the two chips each send data to the respective controlled display area through the SPI signal at the same time. However, the disadvantages are that there still remains delay in the gate drive signals among the plurality of chips as well as different transmission paths of each chip, and it will further increase the production cost since a memory is added to each chip.